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Systematic Design Centering of Continuous Time Oversampling Converters

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Abstract

Clock jitter is a fundamental problem in continuous-time Δ Σ modulators. While many approaches have been proposed to deal with this problem, finite-impulse-response (FIR) feedback is perhaps the most effective. It turns out that FIR feedback has other benefits—it improves the modulator's linearity for a given power dissipation, reduces the effect of the quantizer's data-dependent jitter, and enables the use of chopping "for free." It is an architectural technique that combines the benefits of single-bit and multi-bit operation, and has proven itself to be robust and scalable, applicable to Δ Σ data converters targeting a variety of specifications, and across process nodes. This work reviews the key challenges encountered in the design of high performance delta-sigma data converters, and describes the role of FIR feedback in addressing these challenges. The prospect of using FIR feedback to achieve wide bandwidths is examined, and promising directions are reviewed.

Keywords

  • Oversampling
  • FIR filter
  • Jitter
  • Excess delay
  • Compensation

Notes

  1. 1.

    This is similar to compensating a CTΔ ΣM for excess delay, where coefficient tuning and a direct path around the quantizer is usually needed [2, 20].

  2. 2.

    Sampling rate of 1 Hz.

  3. 3.

    The idea is the same as introducing zeros in a loop to stabilize a feedback system. In the time-domain, this corresponds to adding a derivative(s).

References

  1. J. Cherry, W.M. Snelgrove, Clock jitter and quantizer metastability in continuous-time delta-sigma modulators. IEEE Trans. Circuits Syst. II. Analog Digit. Signal Process 46(6), 661–676 (1999)

    CrossRef  Google Scholar

  2. J.A. Cherry, Theory, practice, and fundamental performance limits of high speed data conversion using continuous-time delta-sigma modulators, Ph.D. dissertation, Carleton University, 1998

    Google Scholar

  3. M. Ortmanns, F. Gerfers, Y. Manoli, A continuous-time Σ Δ modulator with reduced sensitivity to clock jitter through SCR feedback. IEEE Trans. Circuits Syst. I Reg. Papers 52(5), 875–884 (2005)

    MathSciNet  CrossRef  Google Scholar

  4. S. Pavan, Alias rejection of continuous-time delta-sigma modulators with switched-capacitor feedback DACs. IEEE Trans. Circuits Syst. I Reg. Papers 58(2), 233–243 (2011)

    CrossRef  Google Scholar

  5. O. Oliaei, Sigma-delta modulator with spectrally shaped feedback. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. 50(9), 518–530 (2003)

    MathSciNet  CrossRef  Google Scholar

  6. B.M. Putter, Σ Δ ADC with finite impulse response feedback DAC, in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (IEEE, Piscataway, 2004), pp. 76–77

    Google Scholar

  7. S. Loeda, J. Harrison, F. Pourchet, A. Adams, A 10/20/30/40 MHz feedforward FIR DAC continuous-time Δ Σ ADC with robust blocker performance for radio receivers. IEEE J. Solid-State Circuits 51(4), 860–870 (2016)

    CrossRef  Google Scholar

  8. P. Shettigar, S. Pavan, Design techniques for wideband single-bit continuous-time Δ Σ modulators with FIR feedback DACs. IEEE J. Solid-State Circuits 47(12), 2865–2879 (2012)

    CrossRef  Google Scholar

  9. D.K. Su, B.A. Wooley, A CMOS oversampling D/A converter with a current-mode semidigital reconstruction filter. IEEE J. Solid-State Circuits 28(12), 1224–1233 (1993)

    CrossRef  Google Scholar

  10. P. Shettigar, S. Pavan, A 15 mW 3.6 GS/s CT delta-sigma ADC with 36 MHz bandwidth and 83 dB dynamic range in 90 nm CMOS , in Digest of Technical Papers, International Solid State Circuits Conference (2008), pp. 498–631

    Google Scholar

  11. V. Srinivasan, V. Wang, P. Satarzadeh, B. Haroun, M. Corsi, A 20 mW 61 dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6 GHz in 45 nm CMOS, in Digest of Technical Papers, International Solid-State Circuits Conference (ISSCC) (2012), pp. 158–160

    Google Scholar

  12. S. Zeller, C. Muenker, R. Weigel, U. Ussmueller, A 0.039 mm2 inverter-based 1.82 mW 68.6 dB-SNDR 10 MHz-BW CT-Δ Σ-ADC in 65 nm CMOS using power-and area-efficient design techniques. IEEE J. Solid-State Circuits 49(7), 1548–1560 (2014)

    Google Scholar

  13. Y. Zhang, C.-H. Chen, T. He, G.C. Temes, A continuous-time delta-sigma modulator for biomedical ultrasound beamformer using digital ELD compensation and FIR feedback. IEEE Trans. Circuits Syst. I Reg. Papers 62(7), 1689–1698 (2015)

    MathSciNet  CrossRef  Google Scholar

  14. S. Billa, A. Sukumaran, S. Pavan, Analysis and design of continuous-time delta–sigma converters incorporating chopping. IEEE J. Solid-State Circuits 52(9), 2350–2361 (2017)

    CrossRef  Google Scholar

  15. A. Jain, S. Pavan, A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔ ΣM with time-interleaved FIR feedback, in Proceedings of the Symposium on VLSI Circuits (IEEE, Piscataway, 2016), pp. C256–C257

    Google Scholar

  16. A. Sukumaran, S. Pavan, Design techniques for audio single-bit continuous-time delta sigma modulators with FIR feedback. IEEE J. Solid State Circuits 47(11), 1–15 (2014)

    Google Scholar

  17. J. Gealow, M. Ashburn, C.-H. Lou, S. Ho, P. Riehl, A. Shabra, J. Silva, Q. Yu, A 2.8 mW Δ Σ ADC with 83 dB DR and 1.92 MHz BW using FIR outer feedback and TIA-based integrator, in Proceedings of the Symposium on VLSI Circuits (IEEE, Piscataway, 2011), pp. 42–43

    Google Scholar

  18. S. Pavan, Finite-impulse-response (FIR) feedback in continuous-time delta-sigma converters, in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC) (IEEE, Piscataway, 2018), pp. 1–8

    Google Scholar

  19. S. Billa, A. Sukumaran, S. Pavan, A 280μW 24kHz-BW 98.5 dB-SNDR chopped single-bit CTDSM achieving < 10 Hz 1∕f noise corner without chopping artifacts, in Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC) (IEEE, Piscataway, 2016), pp. 276–277

    Google Scholar

  20. S. Pavan, Excess loop delay compensation in continuous-time delta-sigma modulators. IEEE Trans. Circuits Syst. II Express Briefs 55(11), 1119–1123 (2008)

    CrossRef  Google Scholar

  21. S. Pavan, Continuous-time delta-sigma modulator design using the method of moments. IEEE Trans. Circuits Syst. I Reg. Papers 61(6), 1629–1637 (2014)

    CrossRef  Google Scholar

  22. S. Pavan, R. Schreier, G. Temes, Understanding Delta-Sigma Data Converters, 2nd edn. (Wiley-IEEE Press, Piscataway, 2017)

    Google Scholar

  23. S. Pavan, Systematic design centering of continuous time oversampling converters. IEEE Trans. Circuits Syst. II Express Briefs 57(3), 158–162 (2010)

    CrossRef  Google Scholar

  24. S. Ho, C.-L. Lo, J. Ru, J. Zhao, A 23 mW, 73 dB dynamic range, 80 MHz BW continuous-time delta-sigma modulator in 20 nm CMOS. IEEE J. Solid-State Circuits 50(4), 908–919 (2015)

    CrossRef  Google Scholar

  25. Y.-S. Shu, S. Ho, H.-H. Chen, B. Narasimhan, K.-H.L. Loh, Signal processing and analog/RF circuit design: cross-discipline interactions and technical challenges, in APSIPA Transactions on Signal and Information Processing, vol. 5 (Cambridge University Press, Cambridge, 2016)

    Google Scholar

  26. J.-K. Cho, S. Woo, A 6-mW, 70.1-dB SNDR, and 20-MHz BW continuous-time sigma-delta modulator using low-noise high-linearity feedback DAC. IEEE Trans. Very Large Scale Integr. Syst. 25(5), 1742–1755 (2017)

    CrossRef  Google Scholar

  27. D.-Y. Yoon, S. Ho, H.-S. Lee, An 85dB-DR 74.6 dB-SNDR 50MHz-BW CT MASH Δ Σ modulator in 28nm CMOS, in Proceedings of the International Solid-State Circuits Conference (ISSCC) (IEEE, Piscataway, 2015), pp. 1–3.

    Google Scholar

  28. D.-Y. Yoon, S. Ho, H.-S. Lee, A continuous-time Sturdy-MASH Δ Σ modulator in 28 nm CMOS. IEEE J. Solid-State Circuits 50(12), 2880–2890 (2015)

    CrossRef  Google Scholar

  29. R. Kaald, T. Eggen, T. Ytterdal, A 1 MHz BW 34.2 fJ/step continuous time delta sigma modulator with an integrated mixer for cardiac ultrasound. IEEE Trans. Biomed. Circuits Syst. 11(1), 234–243 (2017)

    CrossRef  Google Scholar

  30. A. Jain, S. Pavan, Continuous-time delta-sigma modulators with time-interleaved FIR feedback. IEEE Trans. Circuits Syst. I Reg. Papers 65(2), 434–443 (2018)

    MathSciNet  CrossRef  Google Scholar

  31. C.C. Enz, G.C. Temes, Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization. Proc. IEEE 84(11), 1584–1614 (1996)

    CrossRef  Google Scholar

  32. S. Pavan, Analysis of chopped integrators, and its application to continuous-time Delta-Sigma modulator design. IEEE Trans. Circuits Syst. I Reg. Papers 64(9), 1953–65 (2017)

    CrossRef  Google Scholar

  33. D.R. Welland, B.P. Del Signore, D.A. Kerth, Delta-sigma analog-to-digital converter with chopper stabilization at the sampling frequency, US Patent 5,039,989, 1991

    Google Scholar

  34. R. Theertham, S. Pavan, Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators. IEEE Trans. Circuits Syst. I. Reg. Papers 66(8), 2831–2842 (2019)

    CrossRef  Google Scholar

  35. R. Theertham, P. Kootala, S. Billa, S. Pavan, A 24mW Chopped CTDSM Achieving 103.5 dB SNDR and 107.5 dB DR in a 250kHz Bandwidth. Proceedings of the Symposium on VLSI Circuits, Kyoto, C226–C227 (2019)

    Google Scholar

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Authors and Affiliations

  1. Indian Institute of Technology Madras, Chennai, India

    Shanthi Pavan

Corresponding author

Correspondence to Shanthi Pavan .

Editor information

Editors and Affiliations

  1. Department of Physics "G. Occhialini", University of Milan-Bicocca, Milan, Italy

    Dr. Andrea Baschirotto

  2. Eindhoven University of Technology, Eindhoven, Noord-Brabant, The Netherlands

    Pieter Harpe

  3. Delft University of Technology, Delft, Zuid-Holland, The Netherlands

    Kofi A. A. Makinwa

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Pavan, S. (2020). Continuous-Time Delta-Sigma Converters with Finite-Impulse-Response (FIR) Feedback. In: Baschirotto, A., Harpe, P., Makinwa, K. (eds) Next-Generation ADCs, High-Performance Power Management, and Technology Considerations for Advanced Integrated Circuits. Springer, Cham. https://doi.org/10.1007/978-3-030-25267-0_5

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